Multicore Hardware-Software Design and Verification Techniques


by

Pao-Ann Hsiung, Yean-Ru Chen, Chao-Sheng Lin

DOI: 10.2174/97816080522571110101
eISBN: 978-1-60805-225-7, 2011
ISBN: 978-1-60805-685-9



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Indexed in: Scopus

The surge of multicore processors coming into the market and on users’ desktops has made parallel computing the focus of attention...[view complete introduction]

Table of Contents

Foreword

- Pp. i

Ahmed Jerraya

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Preface

- Pp. ii-iv (3)

Pao-Ann Hsiung, Yean-Ru Chen and Chao-Sheng Lin

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List of Contributors

- Pp. v-vi (2)

Pao-Ann Hsiung, Yean-Ru Chen and Chao-Sheng Lin

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Acknowledgements

- Pp. vii

Pao-Ann Hsiung, Yean-Ru Chen and Chao-Sheng Lin

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Affinity and Distance-Aware Thread Scheduling and Migration in Reconfigurable Many-Core Architectures

- Pp. 3-18 (16)

Fadi N. Sibai

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On the Design of Multicore Architectures Guided by a Miss Table at Level-1 and Level-2 Caches to Improve Predictability and Performance/Power Ratio

- Pp. 19-32 (14)

Abu Asaduzzaman and Fadi N. Sibai

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TRoCMP: An Approach to Energy Saving for Multi-Core Systems

- Pp. 33-60 (28)

Long Zheng, Mianxiong Dong, Minyi Guo, Song Guo, Kaoru Ota and Jun Ma

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Model-Driven Multi-core Embedded Software Design

- Pp. 61-77 (17)

Chao-Sheng Lin, Pao-Ann Hsiung, Chih-Hung Chang, Nien-Lin Hsueh, Chorng-Shiuh Koong, Chih-Hsiong Shih, Chao-Tung Yang and William C.-C. Chu

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Automatic High-Level Code Generation for Multi-Core Processors in Embedded Systems

- Pp. 78-92 (15)

Yu-Shin Lin, Shang-Wei Lin, Chao-Sheng Lin, Chun-Hsien Lu, Chia-Chiao Ho, Yi-Luen Chang, Bo-Hsuan Wang and Pao-Ann Hsiung

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Index

- Pp. 93-95 (3)

Pao-Ann Hsiung, Yean-Ru Chen and Chao-Sheng Lin

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Foreword

Though the transistor density in a single chip keeps doubling every 18 months according to the Moore’s law from 1965, the increasing of clock frequency has hit its ceiling owing to physical constraints around 2003. Memory wall, instruction-level parallelism (ILP) wall, and power wall are the main obstacles for high clock speed in a microprocessor. To overcome the barriers and keep exploiting the advantages from Moore’s law, microprocessor vendors have started providing multi-core architectures that can increase the computing power for application acceleration. Today multi-core architectures have been proved to be ideal solutions by being adopted in a wide range from the server, desktop, and laptop to the embedded systems and digital signal processing design.

Though multi-core systems have brought us the benefits of higher computing power and low power consumption, it has also created new challenges in hardware architecture design and software application design and analysis. For the hardware architecture, the design of memory distribution and cache hierarchy is important, which may affect the cache hit rate, memory access latency, thread scheduling, and migration strategies. For software design, operating systems, parallel algorithms and libraries, and language extensions are being developed to support parallel programming models based the multi-threaded programming paradigm. Application designers need to analyze the computationally intensive tasks in an application and decompose them into smaller logical tasks to be managed by parallel algorithms (libraries). All the issues arising from each design level may affect the application performance on multi-core systems.

This ebook, Multicore Hardware-Software Design and Verification Techniques, tries to give the readership an overview on the major issues of engineering in multi-core systems and the inception of marching into the multi-core world. Chapters 1, 2, and 3 help readers to assimilate the major issues in system design due to the characteristics of diverse multi-core architectures. Chapters 4 and 5 introduce the issues in application design and analysis, which are targeted for multi-core systems. This book is designed to give the readers a consolidated and hierarchal concept from the underlying multi-core architectural characteristics to the high-level software and application design. I believe readers will not only learn from this book, but will be of high reference value.

Ahmed Jerraya
CEA-LETI, MINATEC
France


Preface

The surge of multicore processors coming into the market and on users’ desktops has made parallel computing the focus of attention once again. At this focal point of urgency and immaturity, this ebook is being put forward as a platform for immediate collection of state-of-the-art technologies in both hardware and software designs for multicore computing.

READERSHIP

It is our hope that this ebook will be of immense help to system and software engineers, including both experts and non-experts in multicore processor design and software programming. Potential readership is as follows:

  1. The vast majority of software programmers who are perplexed by the rapidly increasing number of cores in a processor and by the parallel computing techniques required of them
  2. Educators in the hardware and software fields, who need to catch up with multicore programming so that engineers entering the industry already have the basic art of parallel computing
  3. Researchers in the parallel computing field, who need to ensure that their background knowledge in parallel computing can be adapted to multiple on-chip cores and not only distributed computing clusters


There are totally five chapters included in this ebook, which were selected from a number of submissions and reviewed thoroughly. Some of the chapters were invited from prominent groups of researchers. The chapters mainly deal with issues of thread scheduling, energy saving, and model-driven software generation and verification. In the following, we will briefly describe each of the chapters included in this issue of the ebook.

ORGANIZATION

The first chapter focuses on thread scheduling for many-core architectures that are interconnected by a 2-dimensional mesh interconnection network. It mainly evaluates thread scheduling and migration techniques through simulation. Core affinity and distance-based migration are the main criteria proposed for high-performance scheduling.

The second chapter focuses on green design with performance improvement for the cache designs in multi-core systems. It evaluates where to place the miss table in a multi-level cache hierarchy. For MPEG4 and FFT algorithms, the authors claim that cache locking at level-1 is more beneficiary than at level-2. Not only is the mean delay per task reduced significantly, but the total power consumption is also reduced drastically.

The third chapter is another chapter on green design, which focuses on how tag reduction for level-1 instruction cache can be performed in multi-core systems. A significant amount of power is saved by the proposed Tag Reduction on CMP (TRoCMP) method.

The fourth chapter is about a multi-core embedded software development framework called VERTAF/Multi-Core (VMC), which encompasses all phases of the design flow, including requirements modeling, design modeling, architecture mapping, code generation, code optimization, testing, and multi-view design repository. Automatic model-driven software development is the main goal of VMC. This is also an open-source project, which has resulted in software tools that are available for research and academia.

The fifth and final chapter in this ebook is mainly about how code can be automatically generated from SysML models that contain user-specified parallelism. All three real-world parallelism, including task parallelism, data parallelism, and data-flow parallelism (such as parallel pipeline) have been addressed in the code generator. The code generator has also been integrated as a part of the VMC framework. Currently, it supports multiple multi-core platforms including ARM 11 MPCore and Intel quad core. Libraries such as quantum platform (QP) for realizing state machines and Intel’s threading building block (TBB) for realizing parallelism are both supported in the VMC code generator.

EDITOR BIOGRAPHIES

Pao-Ann Hsiung, Ph.D., received his B.S. in Mathematics and his Ph.D. in Electrical Engineering from the National Taiwan University, Taipei, Taiwan, ROC, in 1991 and 1996, respectively. From 1996 to 2000, he was a post-doctoral researcher at the Institute of Information Science, Academia Sinica, Taipei, Taiwan, ROC. From February 2001 to July 2002, he was an assistant professor and from August 2002 to July 2007 he was an associate professor in the Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC. Since August 2007, he has been a full professor.

Dr. Hsiung was the recipient of the 2001 ACM Taipei Chapter Kuo-Ting Li Young Researcher for his significant contributions to design automation of electronic systems. Dr. Hsiung was also a recipient of the 2004 Young Scholar Research Award given by National Chung Cheng University to five young faculty members per year.

Dr. Hsiung is a senior member of the IEEE, a senior member of the ACM, and a life member of the IICM. He has been included in several professional listings such as Marquis' Who's Who in the World, Marquis' Who's Who in Asia, Outstanding People of the 20th Century by International Biographical Centre, Cambridge, England, Rifacimento International's Admirable Asian Achievers (2006), Afro/Asian Who's Who, and Asia/Pacific Who's Who. Dr. Hsiung is an editorial board member of the International Journal of Embedded Systems (IJES), Inderscience Publishers, USA; the International Journal of Multimedia and Ubiquitous Engineering (IJMUE), Science and Engineering Research Center (SERSC), USA; an associate editor of the Journal of Software Engineering (JSE), Academic Journals, Inc., USA; an editorial board member of the Open Software Engineering Journal (OSE), Bentham Science Publishers, Ltd., USA; an international editorial board member of the International Journal of Patterns (IJOP). Dr. Hsiung has been on the program committee of more than 60 international conferences. He served as session organizer and chair for PDPTA'99, and as workshop organizer and chair for RTC'99, DSVV'2000, PDES'2005, WoRMES’2009, and WESQA’2010. He has published more than 200 papers in international journals and conferences. He has taken an active part in paper refereeing for international journals and conferences.

His main research interests include multi-core programming, reconfigurable computing and system design, cognitive radio architecture, System-on-Chip (SoC) design and verification, embedded software synthesis and verification, real-time system design and verification, hardware-software codesign and coverification, and component-based object-oriented application frameworks for real-time embedded systems.

Yean-Ru Chen received the B.S. degree in Computer Science and Information Engineering from the National Chiao Tung University, Hsinchu, Taiwan, ROC in 2002. From 2002 to 2003, she was employed as an engineer in SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan, ROC. She received the M.S. degree in Computer Science and Information Engineering from the National Chung Cheng University, ChiaYi, Taiwan, ROC in 2006. She is currently a Ph.D. candidate in Graduate Institute of Electronics Engineering of National Taiwan University, Taipei, Taiwan, ROC.

Her current research interests include model checking, SAT, SMT, safety-critical systems, network-on-chip (NoC), security-critical systems (role-based access systems) and Multi-Core embedded software.

Chao-Sheng Lin received the B.S. degree in Architecture and Urban Design from Chinese Culture University, Taipei, Taiwan, ROC, in 1998, and the M.S. degree in the Department of Computer Science and Information Engineering from National Chung Cheng University, Chiayi, Taiwan, ROC, in 2007. He is now working toward the PhD degree in the Department of Computer Science and Information Engineering at National Chung Cheng University. He has two-year working experience in software engineering and had been the vice senior software engineer in Synchronous Communication Corp. in Taiwan.

His research interests include formal verification, reconfigurable systems, and multi-core programming.

ACKNOWLEDGMENTS

We greatly appreciate the contributions from all the authors and thanks to Bentham Science Publishers for providing us such great opportunity to publish this ebook.

Pao-Ann Hsiung, Yean-Ru Chen and Chao-Sheng Lin
Taiwan

List of Contributors

Editor(s):
Pao-Ann Hsiung
National Chung Cheng University
Taiwan


Yean-Ru Chen
National Taiwan University
Taiwan


Chao-Sheng Lin
National Chung Cheng University
Taiwan




Contributor(s):
Abu Asaduzzaman
Department of Computer and Electrical Engineering and Computer Science
Florida Atlantic University, Boca Raton
Florida , 33431
USA


Chih-Hung Chang
Department of Information Management
Hsiuping Institute of Technology
Taichung, 310027
Taiwan


Yi-Luen Chang
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


William C.-C. Chu
Department of Computer Science
Tunghai University
Taichung
Taiwan


Mianxiong Dong
School of Computer Science and Engineering, University of Aizu
Aizu-Wakamatsu, 965-8580
Japan
/
Department of Electrical and Computer Engineering
University of Waterloo
Waterloo, N2L, 3G1
Canada


Minyi Guo
Department of Computer Science and Engineering
Shanghai Jiao Tong University
Shanghai, 200020
China


Song Guo
School of Computer Science and Engineering
University of Aizu
Aizu-Wakamatsu, 965-8580
Japan


Chia-Chiao Ho
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Pao-Ann Hsiung
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Nien-Lin Hsueh
Department of Computer Science and Information Engineering
National Chung Cheng University
Taichung
Taiwan


Chorng-Shiuh Koong
Department of Computer and Information Science
National Taichung University
Taichung
Taiwan


Shang-Wei Lin
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Chao-Sheng Lin
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Yu-Shin Lin
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Chun-Hsien Lu
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Jun Ma
School of Computer Science and Engineering
University of Aizu
Aizu-Wakamatsu, 965-8580
Japan


Kaoru Ota
School of Computer Science and Engineering
University of Aizu
Aizu-Wakamatsu, 965-8580
Japan


Fadi N. Sibai
Faculty of Information Technology
UAE University
Al Ain, P. O. Box 17551
UAE


Chih-Hsiong Shih
Department of Computer Science
Tunghai University
Taichung
Taiwan


Bo-Hsuan Wang
Department of Computer Science and Information Engineering
National Chung Cheng University
Taiwan


Chao-Tung Yang
Department of Computer Science
Tunghai University
Taichung
Taiwan


Long Zheng
School of Computer Science and Engineering
University of Aizu
Aizu-Wakamatsu, 965-8580
Japan
/
School of Computer Science and Technology
Huazhong University of Science and Technology
China




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