Towards a Modeling Synthesis of Two or Three-Dimensional Circuits Through Substrate Coupling and Interconnections: Noises and Parasites


by

Christian Gontrand

DOI: 10.2174/97816080582661140101
eISBN: 978-1-60805-826-6, 2014
ISBN: 978-1-60805-827-3



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The number of transistors in integrated circuits doubles every two years, as stipulated by Moore’s law, and this has been the driving ...[view complete introduction]

Table of Contents

Foreword

- Pp. i-ii (2)

G. Ghibaudo

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Preface

- Pp. iii-v (3)

Christian Gontrand

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From 2D to 3D Circuits and Systems

- Pp. 3-35 (33)

Christian Gontrand

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Noise and Parasites in Mixed Circuits

- Pp. 36-110 (75)

Christian Gontrand

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Defects in Microwave Devices

- Pp. 111-141 (31)

Christian Gontrand

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On The Parasitic Electromagnetic Signals

- Pp. 142-171 (30)

Christian Gontrand

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3D Substrate/Interconnect Modeling

- Pp. 172-211 (40)

Christian Gontrand

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Index

- Pp. 212-218 (7)

Christian Gontrand

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Foreword

The doubling of number of transistors in integrated circuits every two years, as stipulated by Moore’s law, has been the driving force for the huge development of microelectronics industry in the past 50 years. The Moore’s law has enabled the enhancement of complexity and density of planar integrated circuits in 2D of all functions on a single chip, resulting in the emergence of real system-on-chip (SOC). On the other hand, the integration of all these functions can be achieved through 3D integration. There are basically three types of 3D integration levels i.e. 3D IC packaging, 3D IC integration, and, 3D Si integration. These schemes are mostly different because the TSV (through-silicon via) applies to 3D IC and Si integrations, but not to 3D IC packaging. The use of TSV, with the new concept in which every chip or interposer could have two surfaces with circuits, is therefore at the heart of 3D IC and Si integration development. Continued technology scaling together with the integration of heterogeneous technologies on a single chip means that device performance should continue to outperform inter-connect and packaging capabilities, which raises several engineering challenges, such as power management, noise isolation, and intra and inter-chip communication. 3D Si heterogeneous integration is probably the right way to go in order to compete with Moore’s law in the frame of the so-called “More than Moore” application field.

In this eBook, Prof. C. Gontrand aims at providing a modeling synthesis of two or three-dimensional circuits with emphasis on noise and parasitic accounting for substrate coupling and interconnection issues.

In chapter 1, the author underlines that, when increasing interconnect densities and rising cost of integrated circuit (IC) manufacturing, 3D architectures for IC integration are a very promising alternative to standard 2D designs, and, that 3D technology is facing many technological challenges, like completion of vertical interconnects (TSV) which ensure the signal transmission, bonding with alignment of functional dies and substrate thinning. However, he also notices that a lot of benefits in circuit performances can be achieved by 3D integration.

In chapter 2, the author discusses the generation of digital parasitics, their propagation through the substrate, and their effects on analog devices. First, he explains how to characterise the substrate noise, in the time and frequency domains, in order to identify the major parameters that control substrate noise generation, propagation, and reception. Second, he investigates the noise impact on analog circuits from a circuit-level point of view.

In chapter 3, the author handles classical methods for noise analysis at a device point of view. They allow identifying a set of microscopic noise sources in terms of carrier velocity and population fluctuations - called diffusion and generation-recombination noise sources, respectively. Then, he evaluates the effect of microscopic fluctuations on voltage or current fluctuations at the device terminals.

In chapter 4, the author deals with propagation and radiative effects, which become more and more important in integrated circuits. Today deep submicron semiconductor devices are operated at very high frequencies (> GHz). This is particularly important for the characterization of interconnected structures loaded at digital and driver levels. Indeed, it is well known that electromagnetic compatibility (EMC) and signal integrity (SI) are strongly affected by the geometry of interconnects and by the possibly complex nonlinear/dynamic behavior of the electronic devices located at their terminations. At this point, the author is undertaking a detailed semiconductor analysis based on the time-domain drift-diffusion model (DDM) in conjunction with electromagnetic model relying on Maxwell's equations.

In the last chapter, the author demonstrates the effectiveness of such a modeling approach, which is validated in a wide frequency range from DC to 20 GHz. Nevertheless, at high frequency, he shows that substrate-coupling effects are no more negligible and must be included in the overall 3D system electrical description. That is why the author eventually proposes a substrate extraction method, based on transmission line method (TLM) or Green functions, to model the substrate network and interconnect entanglement.

G. Ghibaudo
Director of Research at CNRS
Grenoble
France


Preface

This eBook is attached to a reflexion in the development of intelligent devices and tools for cutting-edge applications in Medical Physics and Telecommunications, but also in High Energy Physics. We aim to develop new technologies and algorithms, with a common theme of placing intelligence into data-acquisition, processing and transmission technologies very close to the information source. We consider applications as pixel detectors in the harsh radiation environment, gamma-ray photodetectors, or others applications requiring extremely rapid “front-end” data processing, event selection, efficient transmission, and high-selectivity. Then, three-dimensional (3D) integration seems to be a good way for succeed in this project. 3D integration has emerged as a critical performance enabler for integrated circuits, at a time when the microelectronics industry is faced with unprecedented scaling barriers, which have arisen both due to fundamental physics and economic constraints. 3D integration provides a mechanism for space transformation of the traditional planar implementation of integrated circuits into three-dimensional space. It therefore provides a pathway to extend geometrical scaling for further performance enhancement (More Moore), as well as provide functional diversification (More than Moore) to improve higher-level system operation. At its core, 3D integration is simply the process of vertically stacking of circuits and creating electrical connections between them.

The advent of 3D integration is a direct result of relentless research in research laboratories, industrial and academic, over the last dozen years. Today, 3D integration exists as a diverse set of stacking and vertical interconnection technologies that can take a multitude of forms, with a suitable implementation depending on the application. Nowadays, commercial 3D products already exist, including small form factor image sensors that include through silicon vias (TSV), and recent products, like 3D memory chips, have been built.

The material of this volume is structured in five chapters;

The first one is dedicated to an introduction of 3D integration. A few years ago, an increasing number of publications and conferences had started to focus on this 3D integration. While a few reference books on this emerging field already existed, there was an urgent need, not to talk about some up-to date developments of technologies, treated in recent books, but to highlight crucial electro-physical problems, for instance electro-thermal ones, which could be addressed through the 3D; then, the idea of this eBook emerged. The heart of this eBook is related to noise or parasites, for instance electromagnetic interferences (EMI), oriented towards the 3D integration technologies The eBook covers the substrate noise on a circuit point of view (Chapter 2), like disturbances of digital blocks, power bounces, phase noise in oscillators, as well as device level (Chapter 3) such as carriers or field fluctuations (chapter 4); EMI are considered at both levels: device and circuit. Chapter 5 deals with the entanglement between interconnect and substrate, both of these items being often considered separately, and their electrical parameters extraction.

This eBook can be particularly beneficial to researchers and engineers who are already working or are intended to begin to work on 3D technologies and are aware of leaving to live all entities forming the complex and heterogeneous circuits in a harsh and noisy environment, which are linked but that have to work autonomously.

Acknowledgements

- To some former PhDs or Engineer Students of mine:

Fengyuan SUN, Olivier VALORGE, Mohamed ABOU-EL-ATTA, José-Cruz NUNEZ-PEREZ, Samir LABIOD, Jean-Etienne LORIVAL, Adel BOUAZRA, Chafia YAHIAOUI, Saïda LATRECHE, Francis CALMON, Jacques VERDIER and Pierre-Jean VIVERGE.

- This work is supported by INFIERI (INtelligent Fast Interconnected and Efficient Devices for Frontier Exploitation in Research and Industry) Program and UPM (Union Pour la Méditerranée).

Conflict Of Interest

The author(s) confirm that this eBook content has no conflict of interest.

Christian Gontrand
Université de Lyon, INSA- Lyon, INL, CNRS
France
E-mail: christian.gontrand@insa-lyon.fr

List of Contributors

Author(s):
Christian Gontrand
Université de Lyon, INSA- Lyon INL, CNRS
France




Reviews

Towards a modeling Synthesis of Two or Three Dimensional Circuits Through Substrate Coupling and Interconnections: Noises and Parasites By C. Gontrand
Context of ebook topic

The doubling of number of transistors in integrated circuits every two years, as stipulated by Moore’s law, has been the driving force for the huge development of microelectronics industry in the past 50 years. The Moore’s law has enabled the enhancement of complexity and density of planar integrated circuits in 2D of all functions on a single chip, resulting in the emergence of real system-on-chip (SOC). On the other hand, the integration of all these functions can be achieved through 3D integration. There are basically three types of 3D integration levels i.e. 3D IC packaging, 3D IC integration, and, 3D Si integration. These schemes are mostly different because the TSV (through-silicon via) applies to 3D IC and Si integrations, but not to 3D IC packaging. The use of TSV, with the new concept in which every chip or interposer could have two surfaces with circuits, is therefore at the heart of 3D IC and Si integration development. Continued technology scaling together with the integration of heterogeneous technologies on a single chip means that device performance should continue to outperform inter-connect and packaging capabilities, which rises several engineering challenges, such as power management, noise isolation, and intra and inter-chip communication. 3D Si heterogeneous integration is probably the right way to go in order to compete with Moore’s law in the frame of the so-called “more than Moore” application field.

Objective of ebook

In this ebook, Prof. C. Gontrand aims at providing a modelling synthesis of two or threedimensional circuits with emphasis on noise and parasitic accounting for substrate coupling and interconnections issues.

In chapter 1, the author underlines that, when increasing interconnect densities and rising cost of integrated circuit (IC) manufacturing, 3D architectures for IC integration are a very promising alternative to standard 2D designs, and, that 3D technology is facing many technological challenges, like completion of vertical interconnects (TSV) which ensure the signal transmission, bonding with alignment of functional dies and substrate thinning. However, he is also noticing that a lot of benefits in circuit performances can be achieved by 3D integration.

In chapter 2, the author is discussing on the generation of digital parasitics, their propagation through the substrate, and their effects on analogue devices. First, he is explaining how to characterize the substrate noise, in the time and frequency domains, in order to identify the major parameters that control substrate noise generation, propagation, and reception. Second, he is investigating the noise impact on analogue circuits from a circuit-level point of view.

In chapter 3, the author is handling classical methods for noise analysis at a device point of view. They allow identifying a set of microscopic noise sources in terms of carrier velocity and population fluctuations - called diffusion and generation-recombination noise sources, respectively. Then, he is evaluating the effect of microscopic fluctuations on voltage or current fluctuations at the device terminals.

In chapter 4, the author is dealing with propagation and radiative effects, which become more and more important in integrated circuits. Today deep submicron semiconductor devices are operated at very high frequencies (> GHz). This is particularly important for the characterization of interconnected structures loaded at digital and driver levels. Indeed, it is well known that electromagnetic compatibility (EMC) and signal integrity (SI) are strongly affected by the geometry of interconnects and by the possibly complex nonlinear/dynamic behaviour of the electronic devices located at their terminations. At this point, the author is undertaking a detailed semiconductor analysis based on the time-domain drift-diffusion model (DDM) in conjunction with electromagnetic model relying on Maxwell's equations.

In the last chapter 5, the author demonstrates the effectiveness of such a modelling approach, which is validated in a wide frequency range from DC to 20 GHz. Nevertheless, at high frequency, he is showing that substrate-coupling effects are no more negligible and must be included in the overall 3D system electrical description. That is why the author is eventually proposing a substrate extraction method, based on transmission line method (TLM) or Green functions, to model the substrate network and interconnect entanglement.

In conclusion, the ebook by Prof. C. Gontrand is very well written, has a very good content and is very much in line with the needs for present and future interconnects and substrate coupling effects in modern integrated circuits. I fully recommend its publication.

Reviewed by Prof. G. Ghibaudo
Director of research at CNRS (Grenoble, France)


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