Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

Volume 1

by

Rasit O. Topaloglu

DOI: 10.2174/97816080507411110101
eISBN: 978-1-60805-074-1, 2011
ISBN: 978-1-60805-695-8



Indexed in: Scopus, EBSCO.

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel len...[view complete introduction]
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Noise-Driven In-Package Decoupling Capacitor Optimization for Power Integrity

- Pp. 167-188 (22)

Yiyu Shi, Hao Yu and Lei He

Abstract

Off-chip decoupling capacitor (decap) allocation is a demanding task during package and chip co-design. Most existing optimization approaches use the input impedance of package as the constraints. However, our research indicates that such practice may lead to large overdesign, and better solutions can be achieved when noise derived from the time-domain waveform is used as the constraint. To illustrate the point, we start with a basic algorithm using simulated annealing (SA) to minimize the total cost of decoupling capacitors under the constraints of worst case noise. The key enabler for efficient optimization with SA is an incremental worst-case noise computation based on FFT over incremental impedance matrix evaluation. Simple as it is, the complexity of SA still limits the applicability of the method, especially in the presence of large numbers of I/O counts and large numbers of legal decap positions for modern packages. To address this issue, we further propose a fast decoupling capacitor allocation method which uses spectral clustering and partitioning, localized macromodeling and sensitivity based iterative optimization to speedup the decap allocation process. We experimentally demonstrate our methods using package designs from industry

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