Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits

Volume 1

by

Rasit O. Topaloglu

DOI: 10.2174/97816080507411110101
eISBN: 978-1-60805-074-1, 2011
ISBN: 978-1-60805-695-8



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Indexed in: Scopus, EBSCO.

The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel len...[view complete introduction]

Table of Contents

Foreword

- Pp. i-iii (3)

Andrew B. Kahng

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Preface

- Pp. iv

Rasit O. Topaloglu and Peng Li

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List of Contributors

- Pp. v

Rasit O. Topaloglu and Peng Li

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Acknowledgements

- Pp. vi

Rasit O. Topaloglu and Peng Li

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A Brief Overview of Lithographic Advancements in the Last Decade with a Focus on Double Patterning

- Pp. 3-20 (18)

Jongwook Kye and Rasit O. Topaloglu

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Interconnect Variability and Performance Analysis

- Pp. 21-39 (19)

Rasit Onur Topaloglu, Zhuo Feng and Peng Li

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Compact Modeling for NBTI and CHC Effects

- Pp. 40-60 (21)

Wenping Wang, Vijay Reddy, Srikanth Krishnan and Yu Cao

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Probability Propagation and Yield Optimization for Analog Circuits

- Pp. 61-80 (20)

Rasit O. Topaloglu, Guo Yu and Peng Li

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Compact Modeling of Engineered Strain

- Pp. 81-119 (39)

Richard Q. Williams

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Chip-Level Statistical Leakage Modeling and Analysis

- Pp. 120-148 (29)

Sheldon X.-D. Tan and Ruijing Shen

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Mathematical Method for VLSI Thermal Simulation at the System and Circuit Levels

- Pp. 149-166 (18)

Dongkeun Oh, Charlie Chung Ping Chen and Yu Hen Hu

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Noise-Driven In-Package Decoupling Capacitor Optimization for Power Integrity

- Pp. 167-188 (22)

Yiyu Shi, Hao Yu and Lei He

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Index

- Pp. 189-191 (3)

Rasi Onur Topaloglu and Peng Li

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Foreword

Semiconductor integrated circuit design ultimately rests on foundations of modeling, analysis, and optimization. The near-term outlook for the industry includes multiple-patterning for continued pitch scaling, aggressive device mobility enhancements for continued performance scaling, and increasing intrusions of variability and reliability into the design flow. New manufacturing techniques expose effects such as electrical variability, aging, leakage, thermal variations, and noise – which are insufficiently covered by traditional device and interconnect models. Notably, electrical variability arises from multiple manufacturing steps that span lithography, embedded stressors, and rapid thermal annealing. At the same time, improved analyses and optimizations will depend heavily on the understanding and coverage of models for such new effects. To integrate the necessary models into the design cycle, new analysis, estimation, and optimization methodologies are required. For example, variability models are needed in fast chip-scale performance, yield, leakage, and thermal predictions and optimizations, as well as in decoupling capacitor planning for reduced noise. Needless to say, improved understanding of new semiconductor design effects is also needed.

The new book edited by Dr. Rasit O. Topaloglu and Dr. Peng Li targets new and critical challenges in semiconductor integrated circuit design modeling, analysis, and optimization. A key contribution of this book is its presentation of different semiconductor manufacturing models together as a package. This enables circuit designers to holistically understand multiple variability challenges, and optimize their circuits while considering all of these concerns. Furthermore, the book covers the modeling and analysis stack from transistor-level models up to chip-scale effects, thereby providing methods and insights that are not just device-specific, but that also apply at the system level. The book also introduces new manufacturing techniques and effects such as double patterning lithography, transistor aging, and process stress.

Chapter 1, on the subject of lithography, introduces the double patterning lithography process, which may become the process of choice in sub-22 nm logic designs. While there has been specialized literature in the area, it has not targeted designers as its main audience. The incorporation of this topic into the book gives valuable understanding of this technology and the design issues it may bring.

Chapter 2, on the subject of interconnect variability, introduces the impact of double patterning lithography on interconnects, and how parameter reduction techniques can be utilized with such manufacturing effects. While parameter reduction methods have been used since before the 90 nm technology node, electrical impacts from double patterning can be significant in sub-22 nm interconnects. This chapter extends the use of parameter reduction into such new contexts.

Aging has been an issue since 65 nm and is yet to be effectively managed or mitigated by designers. Chapter 3 presents aging models to target this gap. Whereas only high-voltage analog circuits were impacted in the past, in the 32 nm node even digital circuits need to be tuned for aging. This chapter in particular targets modeling aspects of both hot carrier injection and bias temperature instability.

Yield prediction methods encompass both multi-scale non-Gaussian and Pareto-based estimation techniques. The use of performance estimation techniques in conjunction with Pareto-based yield prediction has had practical impact since the 90 nm node, and will continue to be a baseline in circuit design going forward. A detailed treatment of this approach has been missing from the literature. Chapter 4, on the subject of performance estimation and yield prediction, targets this gap with phase-locked loop examples.

Stress models have been used in design since the 65 nm node. Now, however, recentlyintroduced stress sources such as through-silicon vias in 3D integration must be comprehended. Chapter 5 describes stress modeling by IBM and provides a solid review of stress modeling fundamentals, tied to electrical performance in a circuit design context.

Leakage modeling and full-chip estimation is another area of continual challenges since the 90 nm node. Chapter 6, on the subject of leakage, spans not only device-level modeling such as junction-tunnel leakage modeling, but also full-chip estimation techniques including grid-based, spectral, and projection-based statistical methods. As low-power design will remain a central methodology for the foreseeable future, this chapter is a necessary reference for designers.

Thermal analysis tools have been commercially deployed since the 90 nm node. With the introduction of 3D integration, thermal issues gain added prominence in circuit design. Chapter 7 targets thermal modeling. The Green’s function-based full-chip methods and speedup methodologies are a promising basis for scalable, accurate thermal analysis. The chapter furthermore includes comparisons with other techniques such as model order reduction and 3D alternate-direction implicit methods.

Finally, chip-package co-design has been important since the 65 nm node. Chapter 8 targets decoupling capacitor allocation using simulated annealing within a noise-driven methodology. The chapter describes spectral clustering and partitioning methods, along with localized macromodeling and sensitivity-based iterative optimizations – and is accompanied by useful industrial examples.

By bringing together recent topics in design-centric modeling, simulation, and optimization of semiconductor manufacturing effects, including new effects that designers must be aware of in sub-32 nm designs, the book is a valuable and timely contribution to researchers and practitioners in the field of integrated circuit design. Each chapter of this book is written in a way that educates the reader – from foundations and clear exposition to the latest industry status along with key references, pointers, and open problems. The book targets students, professors, as well as designers working in the industry: it provides not only introductory material, but also in-depth treatments with thought-provoking open directions for future research and development. And while it is based on technological data that will be applicable over at least the next five to ten years, its theoretical and methodological contributions will be of value over a much longer time frame.

Andrew B. Kahng, Ph.D.
Professor of Computer Science and Engineering and Electrical and Computer
Engineering
University of California, San Diego, U.S.A.


Preface

The last decade has been very fast-paced for the semiconductor industry and researchers. The industry has transitioned from 130 nm technology all the way down to 32 nm production already, with 22 nm process to be ready in a matter of months. The speed of feature size reduction has brought lithographic, device and interconnect design-related, as well as chipscale design challenges.

Technology scaling has been the driving force for the semiconductor industry in the past several decades. The continuing scaling in the nanometer manufacturing era has introduced profound implications. Today, manufacturing and design can no longer be considered as two independent processes; key technology characteristics and limits must be well understood in the design process. Process variation is a growing concern for devices as well as interconnects in highly scaled digital and analog designs. Furthermore, in lieu of technology and performance scaling, power consumption, device reliability, packaging, and thermal challenges must be properly addressed. Along this line, this book intends to cover the following important topics based on contributions from experts in the field.

Double patterning lithography is now used for critical layers for lithography. This topic, along with an overview of lithography in the past decade, is covered in Chapter 1. Spatial variability has drawn significant attention both in terms of devices as well as interconnects. Chapter 2 targets interconnects and impact of their variability on design. It has been found that bias temperature instability is a very important factor in temporal device reliability and needs to be considered during design. This topic is covered in Chapter 3. Accurate modeling and efficient propagation of variability information to circuit outputs has required attention. We target this topic in Chapter 4. Starting with 65 nm design, stress methods are used to further increase the device mobility. These methods are analyzed in detail in Chapter 5. Increased device leakage has made chip-level power and leakage optimization a must. Hence, Chapter 6 is devoted to leakage. Thermal issues have made chip-level thermal optimization necessary. Such effects will be more pronounced over time. These effects are analyzed in Chapter 7. Packaging considerations became part of the design phase and package design requires an elaborate interaction with the backend of the line process. Chapter 8 targets this topic. While such effects could all be analyzed separately from design in the past, they now all need to be carefully analyzed and optimized for during the chip design stage. These changes have raised designaware modeling as well as methodological and optimization challenges.

Abovementioned necessities have convinced us the need to combine recent modeling, methodology, and optimization activities in these areas into a book. We hope that this book targets these problems and offers viable and long-term solutions.

Sincerely,
Rasit O. Topaloglu, Ph.D.
Peng Li, Ph.D.

List of Contributors

Editor(s):
Rasit O. Topaloglu
GLOBALFOUNDRIES
USA




Co-Editor(s):
Peng Li
Texas A&M University
USA




Contributor(s):
Yu Cao
Arizona State University



Charlie C.P. Chen
National Taiwan University



Zhuo Feng
Michigan Technological University



Lei He
University of California at Los Angeles



Yu H. Hu
University of Wisconsin at Madison



Srikanth Krishnan
Texas Instruments



Jongwook Kye
GLOBALFOUNDRIES



Peng Li
Texas A&M University



Dongkeun Oh
University of Wisconsin at Madison



Vijay Reddy
Texas Instruments



Ruijing Shen
University of California at Riversid



Yiyu Shi
Missouri University of Science and Technology



Sheldon X.-D. Tan
University of California at Riverside



Rasit O. Topaloglu
GLOBALFOUNDRIES



Wenping Wang
Arizona State University



Richard Q. Williams
IBM



Guo Yu
Oracle



Hao Yu
Nanyang Technological University





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